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1 ?2008 integrated device technology, inc. october 2008 dsc-5649/5 port - 1 logic block diagram (2) mask register readback on address lines global master reset for all ports dual chip enables on all ports for easy depth expansion separate upper-word and lower-word controls on all ports 272-bga package (27mm x 27mm 1.27mm ball pitch) and 256-bga package (17mm x 17mm 1.0mm ball pitch) commercial and industrial temperature ranges jtag boundary scan mbist (memory built-in self test) controller features true four-ported memory cells which allow simultaneous access of the same memory location synchronous pipelined device ? 64/32k x 18 organization pipelined output mode allows fast 200mhz operation high bandwidth up to 14 gbps (200mhz x 18 bits wide x 4 ports) lvttl i/o interface high-speed clock to data access 3.0ns (max.) 3.3v low operating power interrupt flags for message passing width and depth expansion capabilities counter readback on address lines 3.3v 64/32k x 18 synchronous fourport? static ram idt70v5388/78 note: 1. a 15 x is a nc for idt70v5378. 2. port 2, port 3, and port 4 logic blocks are similar to port 1 logic blocks. tms tck tdi c lkmbist tdo jtag controller mbist trst 64kx18 memory array port 1 address decode , port 1 interrupt logic int p1 priority decision logic port 1 counter/ address register port 1 mask register port 1 readback register addr. read back r/ w p1 ce 0p1 ce 1p1 clk p1 mrst port 1 i/o control r/ w p1 ub p1 ce 0p1 ce 1p1 lb p1 oe p1 i/o 9p1 - i/o 17p1 i/o 0p1 - i/o 8p1 clk p 1 mrst cntint p1 0 1 1/0 mrst a 0p1 -a 15p1 (1) cntrd p1 mkrd p1 mkld p1 cntinc p1 cntld p1 cntrst p1 5649 drw 01 counter wrap-around control ? internal mask register controls counter wrap-around ? counter-interrupt flags to indicate wrap-around green parts available, see ordering information
2 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges description the idt70v5388/78 is a high-speed 64/32kx18 bit synchronous fourport ram. the memory array utilizes fourport memory cells to allow simultaneous access of any address from all four ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows sys- tems to be designed with very short cycle times. with an input data register and integrated burst counters, the 70v5388/78 has been optimized for applica- tions having unidirectional or bi-directional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1 , permits the on-chip circuitry of each port to enter a very low standby power mode. the idt70v5388/78 provides a wide range of func- tions specially designed to facilitate system operations. these include full-boundary, maskable address counters with associated interrupts for each port, mailbox interrupt flags on each port to facilitate inter-port communications, memory built-in self-test (mbist), jtag support and an asynchronous master reset to simplify device initializa- tion. in addition, the address lines have been set up as i/o pins, to permit the support of cntrd (the ability to output the current value of the internal address counter on the address lines) and mkrd (the ability to output the current value of the counter mask register). for specific details on the device operation, please refer to the functional description and subsequent explanatory sections, beginning on page 21.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 3 pin configuration (4) . 70v5388/78bg bg-272 (2) 272-pin bga top view (3) notes: 1. a 15 x is a nc for idt70v5378. 2. this package code is used to reference the package diagram. 3. this text does not indicate orientation of the actual part marking. 4. package body is approximately 27mm x 27mm x 2.33mm, with 1.27mm ball-pitch. 5. central balls are for thermal dissipation only. they are connected to device v ss . a b c d e f g h j k l m n p r t u v w y i/o 16 p2 lb p1 i/o 17 p2 i/o 15 p2 i/o 13 p2 i/o 11 p2 i/o 9 p2 i/o 14 p2 i/o 12 p2 i/o 10 p2 v dd ub p1 i/o 16 p1 i/o 17 p1 i/o 14 p1 i/o 13 p1 i/o 12 p1 i/o 11 p1 i/o 10 p1 tms i/o 10 p4 tdi i/o 12 p4 i/o 11 p4 i/o 14 p4 i/o 13 p4 i/o 16 p4 i/o 17 p4 i/o 9 p3 i/o 10 p3 i/o 11 p3 i/o 12 p3 i/o 13 p3 i/o 14 p3 i/o 15 p3 i/o 16 p3 i/o 17 p3 ub p4 lb p4 v dd a 14 p1 a 12 p1 a 13 p1 ce 1 p1 v ss ce 0 p1 oe p1 r/ w p1 v ss v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd i/o 15 p1 i/o 9 p1 i/o 9 p4 i/o 15 p4 r/ w p4 ce 0 p4 oe p4 a 13 p4 ce 1 p4 a 15 (1) p4 a 12 p4 a 14 p4 v ss v ss v ss v dd v dd tck tdo a 10 p1 a 11 p1 mkrd p1 cntrd p1 a 7 p1 a 8 p1 a 9 p1 a 5 p1 a 6 p1 v ss cntint p1 cntinc p1 a 3 p1 a 4 p1 mkld p1 cntld p1 cntrd p4 cntint p4 cntinc p4 cntld p4 mkrd p4 a 9 p4 a 6 p4 mkld p4 a 11 p4 a 8 p4 a 5 p4 a 4 p4 a 10 p4 a 7 p4 v ss a 3 p4 v dd a 1 p1 a 2 p1 v dd a 0 p1 clk p1 int p1 cntrst p1 a 0 p2 clk p2 int p2 cntrst p2 v dd a 1 p2 a 2 p2 v ss a 3 p2 a 4 p2 mkld p2 cntld p2 a 5 p2 a 6 p2 v ss cntinc p2 a 7 p2 a 8 p2 a 9 p2 cntint p2 a 10 p2 a 11 p2 mkrd p2 cntrd p2 v dd clk p4 clk p3 v ss cntld p3 cntinc p3 cntint p3 cntrd p3 a 2 p4 cntrst p4 cntrst p3 a 2 p3 mkld p3 a 6 p3 a 9 p3 mkrd p3 a 1 p4 int p4 int p3 a 1 p3 a 4 p3 a 5 p3 a 8 p3 a 11 p3 v dd a 0 p4 a 0 p3 v dd a 3 p3 v ss a 7 p3 a 10 p3 a 12 p2 a 13 p2 v ss oe p2 v ss v ss v ss v ss v dd v dd v dd v dd oe p3 a 13 p3 a 12 p3 v ss v ss v ss v dd v dd a 14 p2 a 15 (1) p2 ce 1 p2 ce 0 p2 r/ w p2 v ss v ss v ss v ss i/o 6 p2 i/o 0 p2 i/o 0 p3 i/o 6 p3 r/ w p3 ce 0 p3 ce 1 p3 a 15 (1) p3 a 14 p3 trst nc i/o 7 p1 i/o 5 p1 i/o 3 p1 i/o 1 p1 v dd ub p2 i/o 8 p2 i/o 4 p2 i/o 2 p2 mrst i/o 2 p3 i/o 4 p3 i/o 8 p3 i/o 1 p4 i/o 3 p4 i/o 5 p4 i/o 7 p4 ub p3 v dd lb p2 i/o 8 p1 i/o 6 p1 i/o 4 p1 i/o 2 p1 i/o 0 p1 i/o 7 p2 i/o 5 p2 i/o 3 p2 i/o 1 p2 i/o 1 p3 i/o 3 p3 i/o 5 p3 i/o 7 p3 i/o 0 p4 i/o 2 p4 i/o 4 p4 i/o 6 p4 i/o 8 p4 lb p3 5649 drw 03 gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) gnd (5) , clkmbist 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a b c d e f g h j k l m n p r t u v w y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 9 / 2 5 / 0 2 a 15 (1) p1
4 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges 70v5388/78bc bc-256 (3) 256-pin bga (4) top view a b c d e g f h j k l m n p r t 1 2 3 4 5 6 7 8 910111213141516 cntint p3 clk p3 cntrst p3 int p3 mkld p3 i/o 10 p4 i/o 14 p4 i/o 13 p3 i/o 9 p3 ub p4 ce 1 p4 lb p4 r/ w p4 ce 0 p4 oe p4 cntrd p4 cntinc p4 cntld p4 mkrd p4 a 0 p4 cntint p4 clk p4 cntrst p4 int p4 mkld p4 a 10 p4 i/o 11 p4 i/o 12 p4 i/o 16 p4 i/o 9 p4 i/o 13 p4 i/o 15 p4 i/o 17 p4 i/o 8 p4 i/o 4 p4 i/o 0 p4 lb p3 r/ w p3 oe p3 i/o 5 p3 i/o 1 p3 lb p2 ce 0 p2 oe p2 i/o 6 p2 i/o 4 p2 i/o 0 p2 i/o 6 p1 i/o 3 p1 i/o 7 p4 i/o 5 p4 i/o 1 p4 i/o 6 p3 i/o 2 p3 ub p2 ce 1 p2 i/o 5 p2 i/o 1 p2 a 15 (1) p2 i/o 8 p1 i/o 4 p1 i/o 0 p1 i/o 6 p4 i/o 3 p4 ce 0 p3 i/o 8 p3 i/o 4 p3 i/o 0 p3 a 13 p3 a 14 p3 mrst i/o 2 p4 a 10 p3 i/o 7 p3 i/o 3 p3 a 11 p3 a 12 p3 a 9 p3 trst clkmbist a 11 p4 a 12 p4 a 13 p4 a 14 p4 a 15 (1) p4 a 9 p4 a 8 p4 a 7 p4 a 6 p4 a 5 p4 a 4 p4 a 3 p4 a 2 p4 a 1 p4 i/o 10 p3 i/o 14 p3 ub p3 ce 1 p3 a 15 (1) p3 cntrd p3 cntinc p3 cntld p3 mkrd p3 a 0 p3 i/o 11 p3 i/o 15 p3 i/o 17 p3 i/o 12 p3 i/o 16 p3 a 8 p3 a 7 p3 a 6 p3 a 5 p3 a 4 p3 a 3 p3 a 2 p3 a 1 p3 i/o 11 p2 i/o 13 p1 i/o 16 p1 tms tck i/o 10 p2 i/o 14 p2 i/o 17 p2 r/ w p2 i/o 7 p2 i/o 3 p2 a 13 p2 a 14 p2 i/o 7 p1 i/o 2 p1 cntrd p2 cntinc p2 cntld p2 mkrd p2 mkld p2 cntint p2 clk p2 cntrst p2 int p2 a 10 p2 a 11 p2 a 12 p2 i/o 5 p1 i/o 1 p1 i/o 12 p2 i/o 15 p2 i/o 13 p2 i/o 16 p2 i/o 9 p2 i/o 8 p2 i/o 2 p2 a 9 p2 a 8 p2 a 7 p2 a 6 p2 a 5 p2 a 4 p2 a 3 p2 a 2 p2 a 1 p2 a 0 p2 i/o 10 p1 i/o 14 p1 ub p1 ce 1 p1 a 15 (1) p1 lb p1 r/ w p1 ce 0 p1 a 13 p1 a 14 p1 oe p1 cntrd p1 cntinc p1 mkrd p1 a 0 p1 cntint p1 cntld p1 cntrst p1 int p1 mkld p1 clk p1 a 10 p1 a 11 p1 a 12 p1 a 9 p1 i/o 11 p1 i/o 15 p1 i/o 12 p1 i/o 17 p1 i/o 9 p1 tdo a 8 p1 a 7 p1 a 6 p1 a 5 p1 a 4 p1 a 3 p1 a 2 p1 a 1 p1 tdi v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd 09/25/02 5649 drw 04 123456 7 8 9 10 11 12 13 14 15 16 a b c d e g f h j k l m n p r t pin configuration (2) 2. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 3. this package code is used to reference the package diagram. 4. this text does not indicate orientation of the actual part-marking. notes: 1. a 15 x is a nc for idt70v5378.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 5 pin definitions port 1 port 2 port 3 port 4 description a 0p1 - a 15p1 (1) a 0p2 - a 15p2 (1) a 0p3 - a 15p3 (1) a 0p4 - a 15p4 (1) address inputs. in the cntrd and mkrd operations, these pins serve as outputs for the internal address counter and the internal counter mask register respectively. i/o 0p1 - i/o 17p1 i/o 0p2 - i/o 17p2 i/o 0p3 - i/0 17p3 i/o 0p4 - i/o 17p4 data bus input/output. clk p1 clk p2 clk p3 clk p4 clock input. the maximum clock input rate is f max . the clock signal can be free running or strobed depending on system requirements. mrst master reset input. mrst is an asycnchronous input, and affects all ports. it must be asserted low ( mrst = v il ) at initial power-up. master reset sets the internal value of all address counters to zero, and sets the counter mask registers for each port to 'unmasked'. it also resets the output flags for the mailboxes and the counter interrupts ( int = cntint = v ih ) and deselects all registered control signals. ce 0p1 , ce 1p1 ce 0p2 , ce 1p2 ce 0p3 , ce 1p3 ce 0p4 , ce 1p4 chip enable inputs. to activate any port, both signals must be asserted to their active states ( ce 0 = v il , ce 1 = v ih ). a given port is disabled if either chip enable is deasserted ( ce 0 = v ih and/or ce 1 = v il ). r/ w pi r/ w p2 r/ w p3 r/ w p4 read/write enable input. this signal is asserted low (r/ w = v il ) in order to write to the fourport memory array, and it is asserted high (r/ w = v ih ) in order to read from the array. lb p1 lb p2 lb p3 lb p4 lower byte select input (i/o 0 - i/o 8 ). asserting this signal low ( lb = v il ) enables read/write operations to the lower byte. for read operations, this signal is used in conjunction with oe in order to drive output data on the lower byte of the data bus. ub p1 ub p2 ub p3 ub p4 upper byte select input (i/o 9 - i/o 17 ). asserting this signal low ( lb = v il ) enables read/write operations to the upper byte. for read operations, this signal is used in conjunction with oe in order to drive output data on the upper byte of the data bus. oe p1 oe p2 oe p3 oe p4 output enable input. asserting this signal low ( oe = v il ) enables the device to drive data on the i/o pins during read operation. oe is an asychronous input. cntld p1 cntld p2 cntld p3 cntld p4 counter load input. asserting this signal low ( cntld = v il ) loads the address on the address lines (a 0 - a 15 (1) ) into the internal address counter for that port. cntinc p1 cntinc p2 cntinc p3 cntinc p4 counter increment input. asserting this signal low ( cntinc = v il ) increments the internal address counter for that port on each rising edge of the clock signal. the counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle). cntrd p1 cntrd p2 cntrd p3 cntrd p4 counter readback input. when asserted low ( cntrd = v il ) causes tha t port to output the value of its internal address counter on the address lines for that port. counter readback is independent of the chip enables for that port. if the port is activated ( ce 0 = v il and ce 1 = v ih ), during the counter readback operation, then the data bus will output the data associated with that readback address in the fourport memory array (assuming that the byte enables and output enables are also asserted). truth table iii indicates the required states for all other counter controls during this operation. the specific operation and timing of this funcion is described in detail in the text. cntrst p1 cntrst p2 cntrst p3 cntrst p4 counter reset input. asserting this signal low ( cntrst = v il ) resets the address counter for that port to zero. cntint p1 cntint p2 cntint p3 cntint p4 counter interrupt flag output . this signal is asserted low ( cntint = v il ) when the internal address counter for that port 'wraps around' from max address [(the counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle)] to address min. as the result of counter increment ( cntint = v il ). the signal goes low for one clock cycle, then automatically resets. 5649 tbl 0 1
6 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges pin definitions (con't.) port 1 port 2 port 3 port 4 description mkld p1 mkld p2 mkld p3 mkld p4 counter mask register load input. asserting this signal low ( mkld = v il ) loads the address on the address lines ( a 0 - a 15 (1) ) into the counter mask register for that port. counter mask register operations are described in detail in the text. mkrd p1 mkrd p2 mkrd p3 mkrd p4 counter mask register readback input . asserting this signal low ( mkrd = v il ) causes that port to output the value of its internal counter mask register on the address lines ( a 0 - a 15 (1) ) for that port. address counter and counter-mask operational table indicates the required states for all other counter controls during this operation. counter mask register readback is independent of the chip enables for that port. if the port is activated ( ce 0 = v il and ce 1 = v ih ) during the counter mask register readback operation, then the data bus will output the data associated with that address in the fourport memory array ( assuming that the byte enables and output enables are also asserted). the specific operation and timing of this function is described in detail in the text . int p1 int p2 int p3 int p4 interrupt flag output. the fourport is equipped with mailbox functions: each port has a specific address wthin the memory array which, when written by any of the other ports, will generate an interrupt flag to that port. the port clears its interrupt by reading that address. the memory location is a valid address for data storage: a full 18-bit word can be stored for recall by the target port or any other port. the mailbox functions and associated interrupts are described in detail in the text. tms jtag input: test mode select trst jtag input: test mode reset (intialize tap controller and reset the mbist controller) tck jtag input: test clock tdi jtag input: test data input (serial) tdo jtag output: test data output (serial) clkmbist mbist input: mbist clock gnd thermal grounds (should be treated like v ss ) v dd core power supply (3.3v) v ss electrical grounds (0v) 5649 tbl 02 note: 1. a 15 x is a nc for idt70v5378.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 7 external address previous internal address internal address used clk cntld cntinc cntrst mkld i/o mode xx0 xx l (3) xd i/o (0) counter reset to address 0 an ap ap xx h l d i/o (p) counter disabled (ap reused) an x an l (3) xh hd i/ o (n) external address used an ap ap hh h hd i/o (p) external address blocked?counter disabled (ap reused) xapap + 1 (5) h l (4 ) hhd i/ o (p+1) (5) counter enabled?internal address generation 5649 tbl 04 truth table ii?address counter & mask control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , lb, ub and oe . 3. cntld and cntrst are independent of all other memory control signals including ce 0 , ce 1 and lb, ub. 4. the address counter advances if cntinc = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , lb, ub . 5. the counter will increment as defined by the counter mask register for that port (default mode is to advance one address on e ach clock cycle). oe clk ce 0 ce 1 ub lb r/ w upper byte i/o 9-1 7 lower byte i/o 0-8 mode x h x x x x high-z high-z deselected?power down x x l x x x high-z high-z deselected?power down x l h h h x high-z high-z all bytes deselected x lhhl lhigh-z d in write to lower byte only x lhl h l d in high-z write to upper byte only x lhl l l d in d in write to both bytes l lhhl hhigh-z d out read lower byte only l lhl hh d out high-z read upper byte only l lhl l h d out d out read both bytes h x x x x x high-z high-z outputs disabled 5649 tbl 03 truth table i?read/write and enable control (1,2,3) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. cntld , cntinc , cntrst = v ih . 3. oe is an asynchronous input signal.
8 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges clk mrst cntrst mkld cntld cntinc cntrd mkrd mode operation xlxxxxxx master- reset counter/address register reset and mask registe r set (resets chip as per reset state definition) h l x x x x x reset counter/address register reset h h l x x x x load load of address lines into mask register h h h l x x x load load of address lines into counter/address register hhhhlxxincrementcounter increment hxxxxlx read- back readback counter on address lines hxxxxhl read- back readback mask register on address lines hh h (3) h h x x hold counter hold 5649 tbl 05 address counter and counter-mask control operational table (any port) (1,2) notes: 1. "x" = "don't care", "h" = v ih , "l" = v il . 2. counter operation and mask register operation is independent of chip enable. 3. mkld = v il will also hold the counter. please refer to truth table ii. recommended operating temperature and supply voltage (1) notes: 1. this is the parameter ta. this is the "instant on" case temperature. symbol parameter min. typ. max. unit v dd supply voltage 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltage (addre ss, contro l & i/o inputs) 2.0 ____ v dd + 150mv (2 ) v v il input low voltage -0.3 (1) ____ 0.8 v 5649 tbl 07 recommended dc operating conditions notes: 1. undershoot of v il > -1.5v for pulse width less than 10ns is allowed. 2. v term must not exceed v dd + 150mv. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 5649 tbl 06
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 9 symbol parameter test conditions 70v5388/78s unit min. max. |i li | input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 10 a |i li | jtag input leakage current (1,2) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current (1) v out = 0v to v dd, outp uts in tri-state mo de ___ 10 a v ol output low voltage i ol = +4ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -4ma, v dd = min. 2.4 ___ v 5649 tbl 10 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 150mv) note: 1. at v dd < 2.0v leakages are undefined. 2. applicable only for tms, tdi and trst inputs. symbol rating commercial & industrial unit v term (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 5623 tbl 06 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 8 pf c out (3 ) output capacitance v out = 3dv 10.5 pf 5649 tbl 09 absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. 3. ambient temperature under dc bias. no ac conditions. chip deselected. capacitance (1) (t a = +25c, f = 1.0mh z ) notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o .
10 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges 70v5388/78s200 com'l only 70v5388/78s166 com'l & ind 70v5388/78s133 com'l & ind 70v5388/78s100 com'l & ind symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (all ports active) ce 1 = ce 2 = ce 3 = ce 4 (5) = v il , outputs disabled, f = f max (1) com'l s 405 470 340 395 275 320 205 240 ma ind s ___ ___ 340 400 275 325 205 245 i sb1 stand by current (all ports - ttl level inputs) ce 1 = ce 2 = ce 3 = ce 4 (5) = v ih, outputs disabled, f = f max (1) com'l s 195 225 160 190 130 155 100 120 ma ind s ___ ___ 160 195 130 160 100 125 i sb2 stand by current (one port - ttl level inputs) ce a = v il and ce b = ce c = ce d = v ih (5) active port, outputs disabled, f=f max (1) com'l s 250 290 210 240 170 195 130 150 ma ind s ___ ___ 210 245 170 200 130 155 i sb3 full standby current (all ports - cmos level inputs) all ports outputs disabled, ce (5) > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com'ls1.5151.5151.5151.515 ma ind s ___ ___ 1.5151.5151.515 i sb4 full standby current (one port - cmos level inputs) ce a < 0.2v and ce b = ce c = ce d > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v active port, outputs disabled, f = f max (1) com'l s 250 290 210 240 170 195 130 150 ma ind s ___ ___ 210 245 170 200 130 155 5649 tbl 1 1 dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 3.3v 150mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. parameters are identical for all ports. 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x - 0.2v "x" represents indicator for appropriate port.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 11 input pulse levels (address & controls) input pulse lev els (i/os ) input ris e/fall time s input timing re fe rence le vels output reference levels output load gnd to 3 . 0v gnd to 3.0v 2ns 1.5v 1.5v figure 1 5649 tbl 12 1.5v 50 ? 50 ? 5649 drw 05 10pf (tester) d ata out , ac test conditions (v ddq - 3.3v) figure 2. typical output derating (lumped capacitive load). figure 1. ac output test load *(for t lz , t hz , t wz , t ow ) ? capacitance (pf) from ac test load ? tcd ( typical, ns) 5649 drw 07 0 1 2 3 4 5 6 7 0 20 40 60 80 100 120 140 160
12 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature range (read and write cycle timing) (v dd = 3.3v 150mv, t a = 0c to +70c) 70v5388/78s200 com'l only 70v5388/78s166 com'l & ind 70v5388/78s133 com'l & ind 70v5388/78s100 com'l & ind symbol parameter min. max. min. max. min. max. min. max. unit f max 2 maximum frequency ____ 200 ____ 166 ____ 133 ____ 100 mhz t cyc2 clock cycle time 5 ____ 6 ____ 7.5 ____ 10 ____ ns t ch2 clock high time 2.0 ____ 2.1 ____ 2.6 ____ 4 ____ ns t cl 2 clock low time 2.0 ____ 2.1 ____ 2.6 ____ 4 ____ ns t sa address setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t sc chip enable setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t sw r/w setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t sd inp ut data setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hd inp ut data hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t sb byte setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hb byte hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t scld cntld setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hcld cntld hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t scinc cntinc setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hcinc cntinc hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t scrst cntrst setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hcrst cntrst hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t scrd cntrd setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hcrd cntrd hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t smld mkld setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hmld mkld hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t smrd mkrd setup time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns t hmrd mkrd hold time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns t oe outpu t enable to data valid ____ 4.0 ____ 4.0 ____ 4.2 ____ 5ns t olz (1 , 5) oe to low-z 1 ____ 1 ____ 1 ____ 1 ____ ns t ohz (1,5) oe to high-z 13.4 13.6 14.2 14.5ns t cd2 clock to data valid ____ 3.0 ____ 3.2 ____ 3.4 ____ 3.6 ns t ca2 clock to counter address readback valid ____ 3.4 ____ 3.6 ____ 4.2 ____ 5ns t cm 2 clock to mask register readback valid ____ 3.4 ____ 3.6 ____ 4.2 ____ 5ns t dc data output hold after clock high 1 ____ 1 ____ 1 ____ 1 ____ ns t ck hz (1,2,5) clock high to output high-z 1 3 1 3 1 3 1 3 ns t cklz (1,2,5) clock high to output low-z 1 ____ 1 ____ 1 ____ 1 ____ ns 5649 tbl 13a
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 13 70v5388/78s200 com'l only 70v5388/78s166 com'l & ind 70v5388/78s133 com'l & ind 70v5388/78s100 com'l & ind symbol parameter min. max. min. max. min. max. min. max. unit interrupt timing t sint clock to int set time ____ 5 ____ 6 ____ 7.5 ____ 10 ns t rint clock to int reset time ____ 5 ____ 6 ____ 7.5 ____ 10 ns t scint clock to cntint set time ____ 5 ____ 6 ____ 7.5 ____ 10 ns t rcint clock to cntint reset time ____ 5 ____ 6 ____ 7.5 ____ 10 ns master reset timing t rs master reset pulse width 7.5 ____ 7.5 ____ 7.5 ____ 10 ____ ns t rs r master reset recovery time 7.5 ____ 7.5 ____ 7.5 ____ 10 ____ ns t ro f master reset to output flags reset time ____ 6.5 ____ 6.5 ____ 6.5 ____ 8ns port to port delays t cc s (3) clock-to-clock setup time 4.5 ____ 5 ____ 6.5 ____ 9 ____ ns jtag timing (4 ) f jtag maximum jtag tap controller frequency ____ 10 ____ 10 ____ 10 ____ 10 mhz t tcyc tck clo ck cy cle time 100 ____ 100 ____ 100 ____ 100 ____ ns t th tck clo ck hig h time 40 ____ 40 ____ 40 ____ 40 ____ ns t tl tck clo ck lo w time 40 ____ 40 ____ 40 ____ 40 ____ ns t js jtag setup 20 ____ 20 ____ 20 ____ 20 ____ ns t jh jtag hold 20 ____ 20 ____ 20 ____ 20 ____ ns t jcd tck clock low to tdo valid (jtag data output) ____ 20 ____ 20 ____ 20 ____ 20 ns t jdc tck clo ck low to tdo invalid (jtag data output hold) 0 ____ 0 ____ 0 ____ 0 ____ ns f bist maximum clkmbist frequency ____ 200 ____ 166 ____ 133 ____ 100 mhz t bh clkmbist high time 2 ____ 2.5 ____ 3 ____ 4 ____ ns t bl clkmbist low time 2 ____ 2.5 ____ 3 ____ 4 ____ ns t jrst jtag reset 50 ____ 50 ____ 50 ____ 50 ____ ns t jrsr jtag reset recovery 50 ____ 50 ____ 50 ____ 50 ____ ns 5649 tbl 13b notes: 1. guaranteed by design (not production tested). 2. valid for both data and address outputs. 3. this parameter defines the time necessary for one port to complete a write and have valid data available at that address for access from the other port(s). attempting to read data before t ccs has elapsed will result in the output of indeterminate data. ac electrical characteristics over the operating temperature range (read and write cycle timing) (v dd = 3.3v 150mv, t a = 0c to +70c) 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. 5. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 1).
14 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 lb , ub (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5649 drw 08 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) , , t sc t hc ce 0(b1) a ddress (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 a ddress (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5649 drw 09 timing waveform of read cycle (2) timing waveform of a multi-device read (1,2) notes: 1. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. cntld = v il , cntinc and cntrst = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , lb , ub = v ih following the next rising edge of the clock. refer to truth table i. 4. addresses do not have to be accessed sequentially since cntld = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if lb , ub was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70v5388/78 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. lb , ub , oe , and cntld = v il ; ce 1(b1) , ce 1(b2) , r/ w , cntinc , and cntrst = v ih . switching waveforms
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 15 clk "a" r/ w "a" address "a" data in"a" clk "b" r/ w "b" address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t ccs (3) t cd2 no match valid no match match match valid 5649 drw 10 t dc r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5649 drw 11 qn qn + 3 t cklz t cd2 data out ce 1 lb, ub t cd2 t ckhz t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) , timing waveform of port a write to port b read (1,2,4) timing waveform of read-to-write-to-read ( oe = v il ) (2) notes: 1. ce 0 , lb , ub , and cntld = v il ; ce 1 , cntinc , cntrst , mrst , mkld , mkrd and cntrd = v ih . 2. oe = v il for port "b", which is being read from. oe = v ih for port "a", which is being written to. 3. if t ccs < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (ie, time from write to val id read on opposite port will be t ccs + 2 t cyc2 + t cd2 ). if t ccs > minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on opposite port will be t ccs + t cyc2 + t cd2 ). 4. all timing is the same for all ports. port "a" may be any port. port "b" is any other port on the device. notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. cntld = v il ; cntinc , and cntrst , mrst , mkld , mkrd and cntrd = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since cntld = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
16 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5649 drw 12 data out qn qn + 4 ce 1 lb , ub oe t ch2 t cl2 t cyc2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) , t cklz t cd2 address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 cntld cntinc t cyc2 t ch2 t cl2 5649 drw 13 t sa t ha t scld t hcld t cd2 t dc read external address read with counter counter hold t scld t hcld t scld t hcld read with counter qn + 1 , timing waveform of read-to-write-to-read ( oe controlled) (2) timing waveform of read with address counter advance (1) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. cntld = v il ; cntinc , cntrst , mrst , mkld , mkrd and cntrd = v ih . 3. addresses do not have to be accessed sequentially since cntld = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows. notes: 1. ce 0 , lb and ub = v il ; ce 1 , cntrst , mrst , mkld , mkrd and cntrd = v ih . 2. if there is no address change via cntld = v il (loading a new address) or cntinc = v il (advancing the address), i.e. cntld = v ih and cntinc = v ih , then the data output remains constant for subsequent clocks.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 17 address an clk data in dn dn + 1 dn + 1 dn + 2 cntld cntinc t ch2 t cl2 t cyc2 5649 drw 14 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t scld t hcld write counter hold write with counter write external address write with counter t sd t hd t scinc t hcinc address an d 0 t ch2 t cl2 t cyc2 q 0 q 1 clk data in r/ w cntrst 5649 drw 15 internal (3) address cntld cntinc t scrst t hcrst t sd t hd t sw t hw execute cntrst write read a 0 read read address n qn an + 1 an + 2 read address n+1 data out t sa t ha a 1 an an + 1 (4) (5) (6) ax t scld t hcld t scinc t hcinc a 0 a 0 a 1 timing waveform of write with address counter advance (1) timing waveform of counter reset (2) notes: 1. ce 0, lb , ub , and r/ w = v il ; ce 1 and cntrst , mrst , mkld , mkrd , and cntrd = v ih. 2. ce 0 , lb , ub = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when cntld = v il and equals the counter value when cntld = v ih . 4. addresses do not have to be accessed sequentially since cntld = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during cntrst operation. a read or write cycle may be coincidental with the counter cntrst cycle: address 0000h will be accessed. extra cycles are shown here simply for clarification. for more information on cntrst function refer to truth table ii. 7. cntinc = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle.
18 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges cntint int 5649 drw 16 mrst all other inputs t rs t rof t rsr all address/ data lines t ch2 t cl2 clk t s (2) inactive active t cyc2 timing waveform of master reset (1) notes: 1. master reset will reset the device. for jtag and mbist reset please refer to the jtag timing specification. 2. t s is the set-up time required for all input control signals.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 19 timing waveform of load and read mask register (1,2,3,4) clk a 0 - a 15 mkld mkrd mask i nternal value t cyc2 t ch2 t cl2 t sa t ha t smld t hmld t smrd t hmld t cklz t ckhz t ca2 (1) (2) a n a n (4) a n a n a n a n a n load mask register value read mask-register value 5649 drw 18 , a n clk a 0 - a 15 cntld cntinc cntrd i nternal address data out t cyc2 t ch2 t cl2 t sa t ha t scld t hcld t scinc t hcinc t cklz t ca2 t ckhz t scrd t hcrd t cd2 t dc (2) (3) a n+2 (4) a n a n+1 a n+2 a n+2 a n+2 load external address read internal address read data with counter 5649 drw 17 , qx- 1 qx qn qn+ 1 qn+ 2 qn+ 2 qn+ 2 a n timing waveform of load and read address counter (1,2,3) notes: 1. ce 0, oe , lb and ub = v il ; ce 1, r/ w , cntrst , mrst , mkld and mkrd = v ih . 2. address in output mode. host must not be driving address bus after time t cklz in next clock cycle. 3. address in input mode. host can drive address bus after t ckhz . 4. this is the value of the address counter being read out on the address lines. notes: 1. address in output mode. host must not be driving address bus after time t cklz in next clock cycle. 2. address in input mode. host can drive address bus after t ckhz . 3. ce 0, oe , lb and ub = v il ; ce 1, r/ w , cntrst , mrst , cntld , cntrd and cntinc = v ih . 4. this is the value of the mask register being read out on the address lines.
20 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges clk external address mkld cntld cntinc counter internal address cntint t cyc2 t ch2 t cl2 t smld t hmld t scld t hcld t scinc t hcinc t scint t rcint 007fh xx7dh a n xx7dh xx7eh xx7fh xx00h xx00h 5649 drw 19 , (2) timing waveform of counter interrupt (1,3) notes: 1. ce 0, oe , lb and ub = v il ; ce 1, r/ w , cntrst , mrst , cntrd and mkrd = v ih. 2. cntint is always driven. 3. cntint goes low as the counter address increments (via cntinc = v il ) past the maximum value programmed into the mask register and 'wraps around' to xx00h cntint stays low for one cycle, then resets. in this example, the mask register was programmed at xx7fh ('x' indicates "don't care"). the counter mask register operations are detailed on page 24. 4. cntrst , mrst , cntrd cntinc , mkrd and mkld = v ih . the mailbox interrupt circuitry relies on the state of the chip enables, the read/write signal, and the address location to generate or clear interrupts as appropriate - other control signals such as oe , lb and ub are "don't care". please refer to truth table iii (page 22) for further explanation. 5. address fffeh is the mailbox location for port 2 of idt70v5388. refer to truth table iii for mailbox location of other ports (page 22). 6. port 1 is configured for a write operation (setting the interrupt) in this example, and port 2 is configured for a read opera tion (clearing the interrupt). ports 1 and 2 are used for an example: any port can set an interrupt to any other port per the operations in truth table iii (page 22). 7. the interrupt flag is always set with respect to the rising edge of the writing port's clock, and cleared with respect to the rising edge of the reading port's clock. clk p1 port-1 a ddress int p2 clk p2 port-2 a ddress t cyc2 t ch2 t cl2 t cyc2 t ch2 t cl2 t sa t ha t sa t ha t sint t rint fffe a n fffe a n+1 a n+2 a n+3 a m a m+1 a m+3 a m+4 5649 drw 20 , (5) (5) (7) timing waveform of mailbox interrupt timing (4,6)
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 21 figure 3. depth and width expansion with idt70v5388/78 functional description depth and width expansion the idt70v5388/78 provides a true synchronous fourport static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal and the duration of the r/ w input signal. this is done in order to offer the fastest possible cycle times and highest data throughput. at 200 mhz, the device supports a cycle time of 5 ns, and provides a pipelined data output of 3.0 ns from clock edge to data valid. four ports operating at 200 mhz, each with a bus width of 18 bits, results in a data throughput rate of nearly 14 gbps. as a true synchronous device, the idt70v5388/78 provides the flexibility to clock each port independently: the ports may run at different frequencies and/or out of synchro- nization with each other. as a true fourport device, the idt70v5388/78 is capable of performing simultaneous reads from all ports on the same address location. care should be taken when attempting to write and read address locations simultaneously: the timing diagrams depict the critical parameter t ccs , which determines the amount of time needed to ensure that the write has successfully been completed and so valid data is available for output. violation of t ccs may produce indeterminate data for the read. two or more ports attempting to write the same address location simultaneously will result in indeterminate data recorded at that address. each port is equipped with dual chip enables, ce 0 and ce 1 . a high on ce 0 or a low on ce 1 for one clock cycle on any port will power down the internal circuitry on that port in order to reduce static power consumption. the multiple chip enables also allow easier banking of multiple idt70v5388/78s for depth expansion configurations. one cycle is required with chip enables reasserted to reactivate the outputs. the idt70v5388/78 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v5388/78 can also be used in applica- tions requiring expanded width, as indicated in figure 3. through combining the control signals, the devices can be grouped as necessary to accommodate applications re- quiring 36-bits or wider. 5649 drw 21 idt70v5388/78 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 16 /a 15 (1) ce 1 ce 0 v dd v dd idt70v5388/78 idt70v5388/78 idt70v5388/78 control inputs control inputs control inputs control inputs ub , lb r/ w , oe , clk, cntld , cntrst , cntinc , note: 1. a 16 is for idt70v5388, a 15 is for idt70v5378.
22 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges the idt70v5388/78 supports mailbox interrupts, facilitating communication among the devices attached to each port. if the user chooses the interrupt function, then each of the upper four address locations in the memory array are assigned as a mailbox for one of the ports: ffffh (7fffh for idt70v5378) is the mailbox for port 1, fffeh (7ffeh for idt70v5378) is the mailbox for port 2, fffdh (7ffdh for idt70v5378) is the mailbox for port 3, and fffch (7ffch for idt70v5378) is the mailbox for port 4. truth table iii details the operation of the mailbox interrupt functions. a given port?s interrupt is set (i.e., int goes low) whenever any other port on the device writes to the given port?s address. for example, port 1?s int will go low if port 2, port 3, or port 4 write to ffffh (7fffh for idt70v5378). the int will go low in relation to the clock on the writing port (see also the mailbox interrupt timing waveform on page 20). if a port writes to its own mailbox, no interrupt is generated. the mailbox location is a valid memory address: the user can store an 18-bit data word at that location for retrieval by the target port. in the event that two or more ports attempt to set an interrupt to the same port at the same time, the interrupt signal will go low, but the data actually stored at that location will be indeterminate. the actual interrupt is generated as a result of evaluating the state of the address pins, the chip enables, and the r/ w pin: if the user wishes to set an interrupt to a specific port without changing the data stored in that port?s mailbox, it is possible to do so by disabling the byte enables during that write cycle. once int has gone low for a specific port, that port can reset the int by reading its assigned mailbox. in the case of port 1, it would clear its int signal by reading ffffh (7fffh for idt70v5378). as stated previously, the interrupt operation executes based on the state of the address pins, the chip enables, and the r/ w pin: it is possible to clear the interrupt by asserting a read to the appropriate location while keeping the output enable ( oe ) or the byte enables deasserted, and so avoid having to drive data on the i/o bus. the int is reset, or goes high again, in relation to the reading port?s clock signal. mailbox interrupts master reset the idt70v5388/78 is equipped with an asynchro- nous master reset input, which can be asserted indepen- dently of all clock inputs and will take effect per the master reset timing waveform on page 18. the master reset sets the internal value of all address counters to zero, and sets the counter mask register on each port to all ones (i.e., completely unmasked). it also resets all mailbox interrupts and counter interrupts to high (i.e., non-asserted) and sets all registered control signals to a deselected state. a master reset operation must be performed after power-up, in order to initialize the various registers on the device to a known state. master reset will reset the device. for jtag and mbist reset please refer to the jtag section on page 25. truth table iii ? ? ? ? ?mailbox interrupt flag operations port 1 (1,2) port 2 (1,2) port 3 (1,2) port 4 (1,2) function r/ w ce a 15- a 0 (4) int r/ w ce a 15- a 0 (4) int r/ w ce a 15- a 0 (4 ) int r/ w ce a 15- a 0 (4) int x x x l l l ffff x l l ffff x l l ffff x set port 1 int flag (3) hlffffhxx x xxx x x x x x xreset port 1 int flag l l fffe x x x x l l l fffe x l l fffe x set port 2 int flag (3) x x x x h l fffe h x x x x x x x x reset port 2 int flag l l fffd x l l fffd x x x x l l l fffd x set port 3 int flag (3) xxxxxxxxhlfffdhxx xxreset port 3 int flag l l fffc x l l fffc x l l fffc x x x x l set port 4 int flag (3) xx x xxx x xxx x x h lfffchreset port 4 int flag 5649 tbl 14 notes: 1. the status of oe is a "don't care" for the interrupt logic circuitry. if it is desirable to reset the interrupt flag on a given port while keep ing the i/o bus in a tri-state condition, then this can be accomplished by setting oe = v ih while the read access is asserted to the appropriate address location. 2. the status of the lb and ub controls are "don't care" for the interrupt circuitry. if it is desirable to set the interrupt flag to a specific port without overwriting the data value already stored at the mailbox location, then this can be accomplished by setting lb = ub = v ih during the write access for that specific mailbox. similarly, if it desirable to reset the interrupt flag on a given port while keeping the i/o bus in a tri-state condition, then this can be accomplished by setting lb = ub = v ih while the read access is asserted to the appropriate address location. 3. the interrupt to a specific port can be set by any one of the other three ports. the appropriate control states for the other three ports are depicted above. in the event that two or more ports attempt to set the same interrupt flag simultaneously via a valid data write, the data stored at t he mailbox location will be indeterminate. 4. a 15 is a nc for idt70v5378, therefore mailbox interrupt addresses are 7fff, 7ffe, 7ffd and 7ffc. address comparison will be for a 0 - a 14 .
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 23 address counter control operations figure 4. logic block diagram for read back operations each port on the idt70v5388/78 is equipped with an internal address counter, to ease the process of bursting data into or out of the device. truth table ii depicts the specific operation of the counter functions, to include the order of priority among the signals. all counter controls are independent of chip enables. the device supports the ability to load a new address value on each access, or to load an address value on a given clock cycle via the cntld control and then allow the counter to increase that value by preset increments on each successive clock via the cntinc control (see also the counter mask operations section that follows). the counter can be suspended on any clock cycle by disabling the cntinc , and it can be reset to zero on any clock cycle by asserting the cntrst control. cntrst only affects the address value stored in the counter: it has no effect on the counter mask register. when the counter reaches the maximum value in the array (i.e., address ffffh for idt70v5388 and address 7fffh for idt70v5378) or it reaches the highest value permitted by the counter mask register, it then ?wraps around? to the beginning of the array. when address min is reached via counter increment (i.e., not as a result of an external address load), then the cntint signal for that port is driven low for one clock cycle, automatically resetting on the next cycle. when the cntrd control is asserted, the idt70v5388/78 will output the current address stored in the internal counter for that port as noted in the load and read address counter timing waveform on page 19. the address will be output on the address lines. during this output, the data i/os will be driven in accordance with the settings of the chip enables, byte enables, and the output enable on that port: the device does not automatically tri-state these pins during the address readback operation. cntrd mkrd cntinc cntld cntrst a ddress read back register mask register counter/ address register memory array addr. read back mkld 5649 drw 22 , (i/o) clk
24 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges counter-mask register figure 5. programmable counter-mask register operation (1) note: 1. the "x's" in this diagram represent the upper bits of the counter. 2. a 15 is a nc for idt70v5378. the internal address counter on each port has an associated counter mask register that allows for configu- ration of the internal address counter on that port. truth table iii groups the operations of the address counter with those of the counter mask register, to include master reset and applicable readback operations. each bit in the mask register controls the corre- sponding bit in the internal address counter: writing a ?1? to a bit in the mask register allows that bit to increment in response to cntinc , while writing a ?0? to a bit masks it (i.e., locks it at whatever value is loaded via cntld ). the mask register is extremely flexible: every bit can be controlled independently of every other bit. the counter simply concat- enates those bits that have not been masked, giving the user great selectivity in determining which portions of the memory array are available to a particular port for burst operations. figure 5 illustrates the operation of the counter mask register in simply constraining a port to a selected portion of the array, specifically addresses 0000h to 00ffh. in step one, the mask register is loaded with 00ffh via mkld (see also the load and read mask register timing wave- form on page 19). in step two, a starting address of 00fd is asserted for the start point of a burst, and the cntinc control is enabled. step three indicates the address counter incrementing to 00ffh. in step four, the internal counter determines that all address values greater than 00ffh have been masked, and so it increments past this ?max? value to 0000h. as a result of reaching 0000h via the cntinc operation, the cntint output for this port is automatically triggered ? it will go low for one clock cycle and then reset. the example depicted in figure 5 is a very simple one: it is also possible to mask non-contiguous bits, such as loading 5555h in the mask register. as stated previously, the address counter simply concatenates all bits that have not been masked and continues to increment those bits in accordance with the cntinc control: in this fashion, if the mask register is set at 5555h and a start address of 0007h is asserted via cntld , the next value the counter will increment to in response to the cntinc control is 0012h, then 0013h, then 0016h, etc. besides supporting precise control of which por- tions of the array are available to a particular port in burst operations, the independent control on the mask register bits also provides excellent flexibility in determining the value by which the counter will increment. for example, setting bit 0 of the mask register to ?0? masks it from counter operation, effectively configuring that port to count by increments of two. this can be very useful in configuring two ports to work in combination, effectively creating a single 36-bit port. thus, port 1 can be configured to count by two starting on even addresses (the start point is asserted via cntld ), and port 2 can be configured to count by two starting on odd addresses (again via cntld ). the two ports together will operate on 36-bit data words, storing half of each word in an even-numbered address, the other half in an odd-numbered address. setting bits 1 and 0 of the mask register on a given port to ?0? configures that port to count 00 00 a 15 (2) a 14 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 7 a 8 cntint l cm r l c d m r m r l m c , s te ste s te ste
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 25 jtag support in increments of four: masking bits 2, 1, and 0 configures that port to count in increments of eight, and so on. the ability to set the increments by which the counters will advance gives the user the ability to interleave memory operations among the ports, minimizing the concerns that a given address might be written by more than one port at any given point in time (an operation that would have indeterminate results). the idt70v5388/78 provides a serial boundary scan test access port . the jtag tables starting on page 29 provide the specific details for the jtag implementation on this device. the idt70v5388/78 executes a jtag test logic reset upon power-up. this power-up reset will initialize the tap controller and mbist controller. in most power environments no further action is required. however, if the user has any concern about the system?s voltage states during power-up, then the user can use the optional trst input as part of a board?s power on reset sequence. the trst pin also provides an alternate means of resetting the jtag test logic when required, and is available for use by external jtag controllers as an asynchronous reset signal. if the user does not plan to rely on the optional trst pin, but wants to use jtag functionality, the trst pin should either be tied high (preferred implementation) or left floating. if jtag operations are not desired, the user has a number of options for disabling the jtag functions. one would be to simply tie tck low, leaving all other jtag pins floating (alternatively, tdi and tms could be tied high). since the device executes a jtag reset upon power-up: with tck tied low, no further clocking of the tap will occur and no jtag operations will take place. alternatively, the user can opt to tie trst low (either in lieu of or in addition to tying tck low) and the tap will be locked in a reset condition, blocking all jtag operations. memory built-in-test operations the idt70v5388/78 is equipped with a self-test function that can be run by the user as the result of a single instruction, implemented via the jtag tap interface. if multiple fourport devices are used on the same board, all can execute mbist simultaneously, facilitating board checkout. the mbist function executes a go-nogo test within the device, which then captures pass-fail information and failure count in a special register called the mbist result register (mrr). upon completion of the test, the mrr can be scanned out via the jtag interface, using the internal scan operation. bit zero of the mrr (mrr[0]) is a don't care. bit one of the mrr (mrr[1])indicates the pass/ fail status: a "0" indicates some sort of failure was noted, while a "1" indicates that the memory array passed. the rest of the mrr contains the total number of failed read cycles in the entire mbist sequence. the idt70v5388/78 mbist function has been supplemented with the ability for the user to force a failure report from the device. this allows the user the flexibility of validating the mbist function itself, by verifying that the device is able to report faults as well as passing results. the two modes of operation, normal mbist testing and forced error reporting, are controlled via the jtag tap interface using the instruction program_mbist_mode_select. for further detail, please refer to the system interface parameters table on page 28. the mbist function executes once the runbist instruction is input via the jtag interface. the entire mbist test will be performed with a deterministic number of tck cycles depending on the tck and clkmbist frequency. this can be calculated by using the following formula: t cyc is the total number of tck cycles required to run mbist. spc is the synchronization padding cycles (typically 4-6 cycles, to accommodate state machine overhead, turn- around cycles, etc.) m is a constant that represents the number of read and write operations required to run the internal mbist algorithms (14,811,136) for both idt70v5388 and idt70v5378. go-nogo testing t cyc = x m + spc, where: t cyc [tck] t cyc [clkmbist]
26 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges c lkmbist mbist controller memory cell tap controller tck tms trst 5649 drw 25 0 bypass register (byr) 32 1 0 instruction register (ir) 25 24 x mbist result register (mrr) 31 29 30 0 identification register (idr) 391 0 tdi selection circuitry (mux) tdo , boundary scan register (bsr) 1 10 mbist mode select register (msr) jtag/bist tap controller block diagram
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 27 tck device inputs (1) / tdi/tms d evice outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t tcyc t jrsr t tl t th 5649 drw 26 , jtag timing specifications notes: 1. device inputs = all device inputs except tdi, tms, and trst . 2. device outputs = all device outputs except tdo. 3. to reset the test (jtag) port without resetting the device, tms must be held low for 5 cycles, or trst must be held low for one cycle.
28 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial temperature ranges instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x31d (1 ) defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5649 tbl 15 identification register definitions instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0111 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0110 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. mbist_mode_select 1010 places the mbist mode register between tdi and tdo. a value of '00' written into this register will allow mbist to run in standard memory test mode, outputting valid results as appropriate via the mbist result register. a value of '11' written into the mbist mode register will force the mbist result register (mrr) to report a result of 'fail'., with 8e0000 failed read cycles noted (i.e., the mrr content = (8e0000h, 0, x). the value of the mbist mode register is not guaranteed at power-up and is not affected by master reset and jtag reset. runbist 1000 invokes mb ist. internally updates mbist result register with go-nogo information and number of is sues. program_mbist_mode_register must be run prior to executing runbist in order to ensure valid results. there is no need to repeat this instruction unless the mode of operation is changed: the mmr will retain its programmed value until overwritten or the device is powered down. int_scan 0100 scans out partial information. places mbist result register (mrr) between tdi & tdo. clamp 0101 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi & tdo. reserved 0010, 0011 several combinations are reserved. do not use codes other than those identified above. private 1001, 1011, 1100, 1101, 1110 several combinations areprivate (for idt internal use). do not use codes other than those identified above. 5649 tbl 17 system interface parameters notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative. register name bit size instruction (ir) 4 mbist mode select register (msr) 2 bypass (byr) 1 id entification (idr) 32 boundary scan (bsr) 392 note (3) mbist result (mrr) 26 5649 tbl 16 scan register sizes note: 1. device id for idt70v5378 is 0x31e.
6.42 idt70v5388/78 3.3v 64/32k x 18 synchronous fourport? static ram industrial and commercial te mperature ranges 29 a power 999 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) bg bc 272-ball bga (bg272-1) 256-ball bga (bc256-1) 200 166 133 100 s standard power xxxxx device type 1152k (64k x 18) 3.3v fourport? ram 576k (32k x 18) 3.3v fourport? ram 70v5388 70v5378 5649 drw 27 speedinmh z g (2) green commercial only commercial & industrial commercial & industrial commercial & industrial a ordering information the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 08/20/02: initial public datasheet 09/25/02: added 0.5m density to datasheet 08/20/03: page 10 changed power numbers in dc electrical characteristics table removed preliminary status 01/31/06: page 1 added green availability to features page 29 added green indicator to ordering information 10/23/08: page 29 removed "idt" from orderable part number corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com notes: 1. contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office.

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